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For synchronous designs, a large portion of the total power consumption of the integrated circuit (IC) is due to the storage elements and the clock distribution. Energy efficiency from the clock elements plays a critical role in low-power circuit design. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges) that was not addressed in previous research. This asynchronous data sampling is explored in detail in this paper by analyzing the mechanisms of several different clock-gated DETFFs. Three special clock-gating strategies are evaluated to mitigate this issue in DETFFs. Each of these three solutions has limitations, and the respective tradeoffs are discussed.