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Instruction cache prefetching with extended BTB

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5 Author(s)
Shuh-An Chi ; Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; R-Ming Shiu ; Jih-ching Chiu ; Si-En Chang
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Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determine the target line to be prefetched based on the current fetched line address. However, as the cache line becomes wider, there may be multiple branches in a cache line which hurdles the decision made by these methods. This paper develops a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches. We call it the branch instruction based (BIB) prefetching. In BIB prefetching, the prefetch information is recorded in an extended BTB. Simulation results show that, the BIB prefetching outperforms the traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average. As the BTB designs become more sophisticated and achieve higher hit and accuracy ratio, the BIB prefetching can achieve higher performance

Published in:

Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on

Date of Conference:

10-13 Dec 1997

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