Hardware support for release consistency with queue-based synchronization

Shared-memory multiprocessors are known to have intrinsic overheads imposed by synchronization and data coherency. Release consistency is a memory consistency model, which alleviates these overheads by relaxing the execution order of a parallel program. This paper proposes techniques to improve the performance of release consistency by combining and QOLB synchronization with write caches. In our scheme, writes in a critical section are deferred with a write cache until a lock variable protecting the critical section is released. On a release, the deferred writes are performed not globally but only to a processor that will execute the critical section exclusively at the next time. To determine the next processor at the execution time, we adopt QOLB primitives as synchronization primitives. We evaluate the performance of our scheme by program driven simulation. Experimental results show that it can improve the performance of shared-memory multiprocessors by reducing read stall time and synchronization stall time.