By Topic

Hardware support for release consistency with queue-based synchronization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jae Bum Lee ; Dept. of Comput. Eng., Seoul Nat. Univ., South Korea ; Chu Shik Jhon

Shared-memory multiprocessors are known to have intrinsic overheads imposed by synchronization and data coherency. Release consistency is a memory consistency model, which alleviates these overheads by relaxing the execution order of a parallel program. This paper proposes techniques to improve the performance of release consistency by combining and QOLB synchronization with write caches. In our scheme, writes in a critical section are deferred with a write cache until a lock variable protecting the critical section is released. On a release, the deferred writes are performed not globally but only to a processor that will execute the critical section exclusively at the next time. To determine the next processor at the execution time, we adopt QOLB primitives as synchronization primitives. We evaluate the performance of our scheme by program driven simulation. Experimental results show that it can improve the performance of shared-memory multiprocessors by reducing read stall time and synchronization stall time

Published in:

Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on

Date of Conference:

10-13 Dec 1997