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Three dimensional (3D) integrated circuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is based on the concept of through-silicon vias (TSV) and vertical stacking of multiple active layers. TSV-based 3D IC's offer significant advantages in performance due to reduction in interconnect lengths, and design flexibility in vertical floor planning. However, a critical challenge for the 3D IC integration is thermal management. In this paper, we present a new analytical 3D model and numerical simulations of the temperature field for the 3D chip using the formalism of inplane orthogonal functions. The model takes into account heat transfer through external surfaces of the chip, inhomogeneous electric heating within the layer (localized heating), inter layer heat transfer with possible inhomogeneous TSV placement and micro channel cooling. Our simulations implement the proposed model and demonstrate its viability and computational efficiency for temperature field optimization.