- 1800-2012 IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
REFERENCES TO OTHER PUBLISHERS
- IEC 61691-1-1/IEEE Std 1076, Behavioural languagesPart 1: VHDL Language Reference Manual.
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A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.