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Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing are reviewed and summarized. A historical overview of observed circuit responses is given that concentrates mainly on memory circuits. Memory devices with single-node upset mechanisms are shown to exhibit multiple cell upsets, and spatially redundant logic latches are shown to upset when charge is collected on multiple circuit nodes in the latch. Impacts on characterizing these effects in models and ground-based testing are presented. The impact of multiple-node charge collection on soft error rate prediction is also presented and shows that full circuit prediction is not yet well understood. Finally, gaps in research and potential future impacts are identified.