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VLSI design for diminished-1 multiplication of integers modulo a Fermat number

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4 Author(s)
M. Benaissa ; Dept. of Electr. & Electron. Eng., Newcastle-upon-Tyne Univ., UK ; A. Pajayakrit ; S. S. Dlay ; A. G. J. Holt

The paper presents two new multiplication algorithms for Fermat number transforms which have improved speed, and in which both the algorithm and the hardware circuitry are simplified. These advantages arise from the properties of the diminished-1 addition, which allow the need to generate a rather complicated initial state to be eliminated. Also, a number represented in the diminished-1 number scheme is always one less than its normal binary value, thus enabling the translation step to be avoided by considering the least significant bit (LSB) of the multiplier as a special case having the value LSB+1. One of the algorithms has already been realised using NMOS VLSI technology. The circuit has been designed hierarchically and uses regular structures and is expandable, which makes it very suitable for VLSI implementation. A logic diagram for realisation of the second algorithm is also given and this it to be implemented using CMOS technology. It is estimated that the time taken to complete modulo F4 multiplication would be 1 mu s.

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IEE Proceedings E - Computers and Digital Techniques  (Volume:135 ,  Issue: 3 )