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Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

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4 Author(s)
Cheoljon Jang ; Dept. of Electron. Comput. Eng., Hanyang Univ., Seoul, South Korea ; Jaehwan Kim ; Byunggyu Ahn ; Jongwha Chong

Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.

Published in:

Computers & Digital Techniques, IET  (Volume:7 ,  Issue: 1 )