By Topic

Timing macromodels for CMOS static set/reset latches and their applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wu, C.-Y. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan ; Li, C. ; Hwang, J.S.

Efficient timing macromodels for CMOS static NAND-type and NOR-type latches are developed, to compute analytically their signal timing under different input state transitions. The timing equations in the macromodels are derived from the effective dominant pole of the linearised large-signal equivalent circuit of a latch under the characteristic-waveform consideration. Through extensive comparisons with SPICE simulations, it is found that the macromodels have a maximum error of 22% for the total propagation delay times of the latches, with different device sizes, capacitive loads, device parameter variations, noncharacteristic-waveform input excitations and input-state transitions. When incorporated with the timing models of CMOS combinational logic gates, the macromodels can also be applied to characterise the signal timing of static sequential integrated circuits. Application examples on two CMOS clocked flip-flops and experimental verifications on a fabricated CMOS master-slave T flip-flop are successfully made to confirm the accuracy and applicability of the developed macromodels. Reasonable accuracy, wide applicable ranges and CPU-time, and memory efficiency have made the macromodels very attractive in many CAD applications.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:135 ,  Issue: 3 )