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A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

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6 Author(s)
Tabasy, E.Z. ; Electr. Eng. Dept., Texas A&M Univ., College Station, TX, USA ; Shafik, A. ; Shan Huang ; Yang, N.H.-W.
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ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm 2 area.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 8 )