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Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect

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3 Author(s)
Hamed Abrishami ; Qualcomm Inc., San Diego, CA, USA ; Safar Hatami ; Massoud Pedram

With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:32 ,  Issue: 6 )