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A 210-GHz Amplifier in 40-nm Digital CMOS Technology

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5 Author(s)
Ko, C.-L. ; Department of Electronic Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan ; Li, C.-H. ; Kuo, C.-N. ; Kuo, M.-C.
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This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:61 ,  Issue: 6 )