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A high-speed and high-resolution Analog-to-Digital Conversion circuit is the crucial part in many physics experiments, data communication, and measurement instrumentation. We present the design and test results on a 1.6-Gsps high-resolution waveform digitizer based on a high-speed AD conversion and time-interleaved technique. Considering the mismatch (gain, offset, and skew) among different ADC channels, we employ real-time correction algorithms integrated in an FPGA to enhance the system performance. In the very high-speed situation, simplification of digital processing algorithms is an important task to guarantee a high processing speed. We proposed a novel correction method based on a fully parallel structure. To achieve good performance, we designed a special jitter-cleaning circuit for the sampling clock and front end coupling circuits for the ADCs, and carefully implemented the hardware circuits to guarantee the signal integrity. Test results indicate that this waveform digitizer achieves a sampling rate of 1.6 Gsps and an ENOB around 11 bits for an input signal from 5 MHz to 150 MHz. The ENOB is still above 10.4 bits for an input up to 300 MHz, with the correction algorithms applied.