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A current-mode approach to CMOS neural network implementation

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4 Author(s)
Watanabe, K. ; Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan ; Wang, L. ; Cha, H.-W. ; Ogawa, S.

CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated independently using 0.6 μm CMOS process have confirmed the wideband signal processing capability owing to a fully current-mode approach. Detailed analyses of measured performances have also given the design criteria for fully parallel implementation

Published in:

Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on

Date of Conference:

10-12 Dec 1997

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