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Continuous-Time \Delta \Sigma Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC

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3 Author(s)
Timir Nandi ; Department of Electrical Engineering, Indian Institute of Technology, Madras, Chennai, India ; Karthikeya Boominathan ; Shanthi Pavan

Conventional continuous-time ΔΣ modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. The efficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18- μm CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:48 ,  Issue: 8 )