By Topic

A systolic architecture for sorting an arbitrary number of elements

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zheng, S.Q. ; Dept. of Comput. Sci., Louisiana State Univ., Baton Rouge, LA, USA ; Olariu, S. ; Pinotti, M.C.

We propose a simple systolic VLSI sorting architecture whose main feature is the pipelined use of a sorting network of fixed I/O size p to sort an arbitrarily large data set of N elements. Our architecture is feasible for VLSI implementation and its time performance is virtually independent of the cost and depth of the underlying sorting network. Specifically, we show that by using our design N elements can be sorted in Θ(N/p log N/p) time without memory access conflicts. We also show how to use an AT2-optimal sorting network of fixed I/O size p to construct a similar systolic architecture that sorts N elements in Θ(N/p log N/plogp) time

Published in:

Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on

Date of Conference:

10-12 Dec 1997