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An object-oriented data cache architecture for programmable parallel digital signal processors

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1 Author(s)
Kneip, J. ; Lab. fur Informationstechnol., Hannover Univ., Germany

The paper describes concept and implementation of a data cache architecture with concurrent conflict free access to shared data for DSPs with parallel, synchronized processing units. It utilizes techniques known from object-oriented software design to achieve efficient and programmer friendly on-chip storage of data. The cache internally uses virtual 1D or 2D address spaces directly assigned to data structures instead of a conventional, linear address space. Data within the cache are distributed to a number of memory banks. Virtual local addresses are used for data location and hit/miss detection to minimize cost and memory latency. The object-oriented cache is fully transparent to programmer and compiler, reduces the amount of address calculations to be performed, exploits the 2D spatial locality typical for image processing algorithms and can be integrated into a standard RISC processor pipeline

Published in:

Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on

Date of Conference:

10-12 Dec 1997

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