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Mapping is the off-line allocation of the tasks that represent a parallelised algorithm across a multiprocessor architecture. In this paper the target architecture is heterogeneous, where a number of computationally disparate processors are integrated within a single network. This paper describes the development of several exploratory mapping algorithms that attempt to minimise the cycle-time of the application algorithms. A simple heuristic is appraised first, followed by an examination of a genetic algorithm (GA) approach. Subsequently, the GA is augmented with several specialised operators in an attempt to improve performance. Finally, a mechanism to adapt the operator probabilities based on their recent performance is introduced. Initially, the GA utilises a simple parallel architecture model. However, this leads to the embedding of the target hardware within the objective function to improve performance. Finally, the effectiveness of these approaches are examined and contrasted, with due consideration of what has been learnt about the nature of the heterogeneous mapping problem.