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Transistor Performance Impact Due to Die–Package Mechanical Stress

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5 Author(s)
Leatherman, G.S. ; Logic Technol. Dev. Quality & Reliability Dept., Intel Corp., Hillsboro, OR, USA ; Hicks, J. ; Kilic, B. ; Pantuso, D.
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Shifts in transistor performance due to mechanical stress resulting from interaction of die, packaging, test socketing, and board mount are discussed. Mechanical-stress-induced transistor drive current shifts are measured indirectly using ring oscillator frequencies. P and N effects are extracted independently using appropriately weighted oscillators, and P/N shifts in opposite directions agree with numerical models, which also predict significant differences between stress states associated with packaged-die test and the final usage configuration. The shifts show systematic variation across the die, raising concerns for predictable circuit performance. An example is SRAM caches, where die-package interactions may degrade VCCmin. The results highlight the need to fully characterize these stress effects in both the test and final usage configurations. These shifts, while significant, can be managed through a combination of package technology, circuit techniques, process optimization, and strategic product floor planning.

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Device and Materials Reliability, IEEE Transactions on  (Volume:13 ,  Issue: 2 )