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Browse Journals & Magazines > Computers and Digital Techniq ...> Volume:135 Issue:1 Help

Systolic array implementation of a decimator and an interpolator

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2 Author(s)
Kwan, H.K. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong ; Okullo-Oballa, T.S.

Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate.

Published in:
Computers and Digital Techniques, IEE Proceedings E  (Volume:135 ,  Issue: 1 )

Date of Publication: Jan 1988

Page(s):
70 - 72
ISSN :
0143-7062
INSPEC Accession Number:
3085418
Product Type:
Journals & Magazines
Date of Current Version :
02 May 2005
Issue Date :
Jan 1988

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