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Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

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8 Author(s)

Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. The authors present a mechanism that reduces excess voltage margin by introducing a critical-path monitor (CPM) circuit that measures available timing margin in real time; coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin; and adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. They first demonstrated this mechanism in an IBM Power7 server and proved its effectiveness in the Power7+ product. Power consumption on the VDD rail was reduced by 11 percent for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events.

Published in:

Micro, IEEE  (Volume:33 ,  Issue: 4 )