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This paper presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130-nm CMOS technology. The die occupies an area of 1930 μm by 1250 μm and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and ±200 ppm clock frequency deviation.