By Topic

SRAM Array Structures for Energy Efficiency Enhancement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Achiranshu Garg ; VIRTUS, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore ; Tony Tae-Hyoung Kim

Energy efficiency is a supreme design concern in many ultralow-power applications. In such applications, static random-access memory (SRAM) plays a significant role in energy consumption due to the high density for evermore increased computing power. This brief explores and analyzes SRAM array structures for energy efficiency improvement. In contrast to the traditional practices where SRAM arrays enclose more rows than columns, this work reveals that better SRAM energy efficiencies can be achieved with a wider SRAM array structure with fewer rows than columns particularly at low supply voltage. The analysis shows that the array structure optimization can improve the energy efficiency up to 38% (64 kbit) and 10% (8 kbit) for the same SRAM bit density and the same supply voltage.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:60 ,  Issue: 6 )