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ECL I/O buffers for BiCMOS integrated systems: a tutorial overview

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2 Author(s)
Pickles, N.S. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Lefebvre, M.

In this paper we describe the methodology for the design and layout of fast BiCMOS ECL (emitter-couped logic) I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature- and supply-voltage-compensated and have nominal rise and fall times of 400 ps

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Education, IEEE Transactions on  (Volume:40 ,  Issue: 4 )