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Single-chip interpolating time counter with 200-ps resolution and 43-s range

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4 Author(s)
Kalisz, J. ; Mil. Tech. Acad., Warsaw, Poland ; Szplet, R. ; Pelka, R. ; Poniecki, A.

In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDC's nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS)

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Instrumentation and Measurement, IEEE Transactions on  (Volume:46 ,  Issue: 4 )