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Planar junctionless transistor with non-uniform channel doping

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3 Author(s)
Mondal, Partha ; Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India ; Ghosh, Bahniman ; Bal, Punyasloka

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.4801443 

We propose a planar junctionless transistor (JLT) in silicon-on-insulator (SOI) with non-uniform channel doping in vertical direction to improve the ON to OFF drain current ratio. In single gate JLT in SOI, a thin device layer is depleted in the off-state from the top of the layer and the leakage current flows through bottom of the device layer, and the leakage current depends on the device layer thickness. We show that the decrease of doping in vertical direction suppresses the leakage current flowing through the bottom of the device by decreasing conductivity at the bottom of the device layer.

Published in:

Applied Physics Letters  (Volume:102 ,  Issue: 13 )

Date of Publication:

Apr 2013

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