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Traversing the VLSI design hierarchy for a new, fast systolic stack

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3 Author(s)
Li, H.F. ; Dept. of Comput. Sci., Concordia Univ., West Montreal, Que., Canada ; Probst, D.K. ; Prasad, R.N.

The design of a new, fast systolic stack is systematically carried out by traversing the qualitatively distinct levels of representation of the VLSI design hierarchy. Included in the overall VLSI design process is a formal verification of design correctness, circuit design and layout, as well as a performance analysis of area, time, clock frequency and design extendability. The novel systolic network has been obtained from a known network by applying a transformation technique based on packing and unpacking data elements into packets; the packet approach is used as a timing optimisation technique to eliminate the slowness of the known network.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:135 ,  Issue: 1 )