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A 2.9 /spl mu/m/sup 2/ embedded SRAM cell with co-salicide direct-strap technology for 0.18 /spl mu/m high performance CMOS logic

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14 Author(s)
Noda, K. ; ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan ; Matsui, K. ; Inoue, K. ; Itani, T.
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We present an embedded SRAM cell in a 0.18 /spl mu/m CMOS technology for the first time. The memory cell size is 2.912 /spl mu/m/sup 2/, which is smaller than any SRAMs previously reported. The fabrication process using a Co-Salicide Direct-Strap is fully compatible with salicide-CMOS for high performance applications with no need for any local interconnects or even contact-implants. In this process, a sidewall spacer is selectively etched at the location for Direct-Strap connection before source-drain implants. To obtain a borderless contact to diffusion, a Si/sub 3/N/sub 4/ Visor is built on shallow trench isolation (STI).

Published in:

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Date of Conference:

10-10 Dec. 1997