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A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

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39 Author(s)
Venkatesan, S. ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; Gelatos, A.V. ; Hisra, S. ; Smith, B.
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A high performance 0.20 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15/spl plusmn/0.04 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized and enable fabrication of 7.6 /spl mu/m/sup 2/ 6T SRAM cells.

Published in:

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Date of Conference:

10-10 Dec. 1997

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