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We explore using pulsed latches for timing optimization in field-programmable gate arrays (FPGAs). Pulsed latches are transparent latches driven by a clock with a nonstandard (i.e., not 50%) duty cycle. As latches are already present on commercial FPGAs, their use for timing optimization can avoid the power or area drawbacks associated with other techniques such as clock skew and retiming. We propose algorithms that automatically replace certain flip-flops with latches for performance gains. Under conservative short path or minimum delay assumptions, our latch-based optimization, operating on already routed designs, provides all the benefit of clock skew in most cases and increases performance by 9%, on average, without area penalties or significant netlist changes. We show that short paths greatly hinder the ability of using pulsed latches, and that further improvements in performance are possible by increasing the delay of certain short paths.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:32 , Issue: 5 )
Date of Publication: May 2013