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Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

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3 Author(s)
Wong, H.-S.P. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Chan, K.K. ; Taur, Y.

In this paper, we report a fabrication method that attains the "ideal" double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated.

Published in:

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Date of Conference:

10-10 Dec. 1997

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