Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Exhaustive testing of stuck-open faults in CMOS combinational circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Bate, J.A. ; Dept. of Comput. Sci., Victoria Univ., BC, Canada ; Miller, D.M.

CMOS circuits present some unique testing problems. Certain physical failures are not adequately represented by the traditional stuck-at fault model. Opens in transistors or their connections, a 'stuck-open' fault, can require a sequence of tests. A number of test schemes employing exhaustive or pseudo-exhaustive input sequences have appeared in the literature. The authors examine the applicability of such a method to the testing of stuck-open faults in CMOS combinational circuits. It is shown that without careful planning an exhaustive test may not detect all stuck-open faults. A universal input sequence which will detect all stuck-open faults is proposed. This sequence corresponds to the Eulerian cycle in a directed hypercube. A circuit which generates such a sequence is outlined.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:135 ,  Issue: 1 )