Skip to Main Content
In the early ASIC design planning phase, clock tree estimation always based on best guess of the ASIC planner. The critical elements such as power, latency and uncommon buffer in synthesized clock network will affect the performance as well as power definition of ASIC full chip specifications. The intend of this paper is to understand the relationship in terms of clock network latency, clock skew, and clock network power with respect to registers count, floor planning aspect ratio, design utilization and clock tree synthesis constraint. Hopefully the finding will benefit the ASIC planner in reducing the power and timing specification guard band due to the clock network.