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Scalable Electrical Compact Modeling for Graphene FET Transistors

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5 Author(s)
Fregonese, S. ; Univ. of Bordeaux, Bordeaux, France ; Magallo, M. ; Maneux, C. ; Happy, H.
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A new scalable electrical compact model for the Graphene FET devices is proposed. Starting from Thiele's quasianalytical model, the equations are modified to be fully compatible with SPICE-like circuit simulation. Compared to Meric et al. model, the charge model is improved. This large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using different measurements from the literature, and furthermore, its scalability is demonstrated.

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Nanotechnology, IEEE Transactions on  (Volume:12 ,  Issue: 4 )