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A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG process

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7 Author(s)
Wakabayashi, H. ; Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan ; Yamamoto, T. ; Tatsumi, T. ; Tokunaga, K.
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High-performance 0.1 /spl mu/m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage current and electrical bridging between the gate electrode and S/D regions are suppressed by this high-quality and highly-selective Si-SEG process. The elevated-salicide 0.1-/spl mu/m CMOS devices have high reliability and high drive current, and are suitable for future high-performance logic LSIs.

Published in:

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Date of Conference:

10-10 Dec. 1997