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Third-harmonic current generation in a CMOS transistor is modeled and analyzed including the effects of large-signal clipping and high-frequency roll-off for the application of millimeter-wave (mm-wave) frequency multipliers. Using the model and introducing harmonic rejection techniques, a wideband 8.5-dBm output-power x9 frequency multiplier from X-band to W-band implemented using a 65-nm CMOS process is designed and characterized. Six transformer coupled differential stages are used, two tripler stages, a Ka-band amplifier, and a three-stage W-band power amplifier (PA). The circuit reaches a saturated output power of 8.5 dBm at 91.8 GHz with a 12.2% bandwidth from 88 to 99.5 GHz. Excellent suppression of unwanted harmonics is achieved with better than 31 dBc across all bandwidth. The core design occupies only 390 μm × 675 μm and consumes 438 mW from a 1.2-/2.4-V supply.