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A comparison of high level synthesis and register transfer level design techniques for custom computing machines

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4 Author(s)
Postula, A. ; Dept. of Electr. & Comput. Eng., Queensland Univ., Brisbane, Qld., Australia ; Abramson, D. ; Ziping Fang ; Logathetis, P.

The most expensive component in the process of building a custom computing machine is the time consuming and highly qualified work of hardware designers. This hinders the wide proliferation of CCMs and pushes this innovative technology into a niche market of research applications. A potential solution to the problem is behavioural or high level synthesis (HLS) which promises the compilation of algorithms into hardware. The experiment reported in this paper was aimed at the evaluation of general purpose HLS tools in building CCMs. We focused on identifying areas where the synthesis methods and tools should be improved in order to cope with CCM's specific design problems. The design case, a specialised computer for the simulation of the sintering process, has been carefully chosen to exhibit the problems that are likely to be encountered in advanced designs for CCMs. Our experiment shows that the HLS tools, when supplied with an appropriate input description, are capable of producing a design not too different from RTL level manual design. HLS needs to be improved, especially regarding loop unwinding, pipelining, and the synthesis of suitable memory configurations. However, many of the required techniques are already available from the field of parallel compilation. The conclusion is that improved HLS tools will bring the performance of compiled CCMs very close to that of manual designs. This can put the high performance of CCM technology at the fingertips of computer programmers without extensive hardware expertise

Published in:

System Sciences, 1998., Proceedings of the Thirty-First Hawaii International Conference on  (Volume:7 )

Date of Conference:

6-9 Jan 1998