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A spread-spectrum clock generator (SSCG) is realized by an under-damping all-digital phase-locked loop (PLL). In this SSCG, the spread-spectrum clocking is achieved by switching the divider without a delta-sigma modulator. By using a digital self-calibration technique, the frequency of this SSCG has a triangular modulation profile and relaxes the process variations. This SSCG is fabricated in a 0.18 μm CMOS process. The measured electro-magnetic interference reduction is 14.37 dB. The measured rms and peak-to-peak jitters are 1.49 ps and 13.33 ps in a PLL mode, respectively. The measured rms and peak-to-peak jitters are 2.67 ps and 19.90 ps in a spread-spectrum modulation, respectively.