By Topic

Development of verification envioronment for SPI master interface using SystemVerilog

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Zhili Zhou ; Key Lab of Integrated Micro-Systems, Peking University Shenzhen Graduate School, China ; Zheng Xie ; Xin'an Wang ; Teng Wang

System-level verification with scalable and reusable components provides a solution for current complex SOC verification and SystemVerilog with OOP is one of the most promising language to develop a complete verification environment with constrained random testing, functional coverage and assertions. In this paper, a uniform verification environment for SPI master interface is developed using SystemVerilog after a comprehensive analysis of the verification plan. The proposed multi-layer testbench is comprised of APB driver, SPI slave, scoreboard, checker, coverage analysis and assertions, which are implemented with different properties of SystemVerilog. Furthermore, constrained random testing vectors are generated automatically and driven into the DUT for higher functional coverage. The verification result shows the effectiveness of the proposed verification environment, which is of great feasibility for further extension and reuse.

Published in:

Signal Processing (ICSP), 2012 IEEE 11th International Conference on  (Volume:3 )

Date of Conference:

21-25 Oct. 2012