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Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

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2 Author(s)
Fanori, L. ; Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden ; Andreani, P.

This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 7 )