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The dual-VDD technique has already been employed in reconfigurable processors to improve energy efficiency. In this brief, a variable dual-VDD method is proposed to reduce power consumption further through varying the level of the lower VDD (VDDL) according to the application on a processor. It finds out the optimum VDDL mainly based on the utilization times of all arithmetic logic unit operations by this application. In this estimation, the analysis of technology and architecture is highly required as well. Static timing analysis and power analysis were performed on the RPU, a reconfigurable processor designed in 65-nm CMOS technology. It is estimated that the proposed method can reduce the power of its reconfigurable array by 32% on average for the applications of GPS, MPEG2, H.264, and audio video coding standard (AVS). If VDDL is fixed at 0.6-0.75 V, the power reduction rate of the reconfigurable array will be 15% less on average. The area penalty of this method is less than 3%.