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A Precision Mismatch Measurement Technique for Integrated Capacitor Array Using a Switched Capacitor Amplifier

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2 Author(s)
Young-Cheon Kwon ; Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea ; Oh-Kyong Kwon

This paper presents a precision mismatch measurement method to characterize an integrated capacitor array. Conventional mismatch measurement methods using floating gate capacitance measurement (FGCM) have measurement error due to the large input-referred noise and the small input signal range of the source follower. In order to improve the measurement accuracy, we propose a new measurement method using a parasitic-insensitive switched capacitor amplifier and the correlated double sampling (CDS) technique. The CDS technique eliminates the measurement error from parasitic capacitances, switching errors, and the offset voltage of the amplifier. In order to verify the proposed method, a test chip was fabricated using a 0.18-μm CMOS process. The chip consists of a 4 × 16 metal-insulator- metal capacitor array and a measurement circuit. The measured standard deviation of the capacitance mismatch, σ(ΔCn/<;C>), ranges from 0.0067% to 0.0130%, and the measured standard deviation of the short-term repeatability, σ(Δ(ΔCn/<;C>)), is 0.0025%. These results show that the measurement accuracy of the proposed method is improved by ten times over that of the FGCM method.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:26 ,  Issue: 2 )