2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving

Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In particular, the occupancy of packet buffer is very low in many cases, especially in core routers, which leads to unnecessary consumption of electric power. To solve this problem, a new buffer architecture called Sliced Packet Buffer was proposed. Dividing a whole buffer into multiple sub buffers (called slices) at the LSI level enables to control power management independently according to its occupancy. However, input traffic rate is another parameter for further power savings, which was not considered so far. In this paper, we propose a Two Dimensional Sliced Packet Buffer which enables power management according to not only the buffer occupancy but also the traffic volume. We also propose a model of accurate performance evaluation on energy consumption in the granularity of operational instruction. Through trace-driven simulations with real traffic, we show that our proposed packet buffer can reduce an average 66% of power consumption when an average input rate is 30%.