By Topic

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

16 Author(s)
Brian Setterberg ; Agilent Technologies, Santa Clara, CA, USA ; Ken Poulton ; Sourja Ray ; Dan J. Huber
more authors

Metastable events in ADC comparators cause large errors that cannot be tolerated in test and measurement applications that record data over extended time intervals. This work utilizes BiCMOS technology to provide high dynamic range analog-to-digital conversion at 2.5GS/s with a metastable error rate of less than one error per year and better than 78dB SFDR over a 1GHz BW.

Published in:

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

Date of Conference:

17-21 Feb. 2013