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High performance routers need to temporarily store a large number of packets in response to congestion. DRAM is typically needed to implement large packet buffers, but the worst-case random access latencies of DRAM devices are too slow to match the bandwidth requirements of high-performance routers. Existing DRAM-based architectures for supporting linespeed queue operations can be classified into two categories: prefetching-based and randomization-based. They are all based on interleaving memory accesses across multiple parallel DRAM banks for achieving higher memory bandwidths, but they differ in their packet placement and memory operation scheduling mechanisms. In this paper, we describe novel reservation-based packet buffer architectures with interleaved memories that take advantage of the known packet departure times to achieve simplicity and determinism. The number of interleaved DRAM banks required to implement the proposed packet buffer architectures is independent of the number of logical queues, yet the proposed architectures can achieve the performance of an SRAM implementation. Our reservation-based solutions are scalable to growing packet storage requirements in routers while matching increasing line rates.