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Cache-Conscious Thread Scheduling for Massively Multithreaded Processors

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3 Author(s)

Highly multithreaded architectures introduce another dimension to fine-grained hardware cache management. The order in which the system's threads issue instructions can significantly impact the access stream seen by the caching system. This article studies a set of economically important server applications and presents the cache-conscious wavefront scheduling (CCWS) hardware mechanism, which uses feedback from the memory system to guide the issue-level thread scheduler and shape the access pattern seen by the first-level cache.

Published in:

Micro, IEEE  (Volume:33 ,  Issue: 3 )

Date of Publication:

May-June 2013

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