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This paper presents a measurement setup for digital output buffers' characterization. This is of recognized importance for the integrated circuit industry and has rarely been addressed in the literature related to output buffer modeling. Currently, the model extraction is typically performed by simulating the transistor-level model of the device, which raises important issues regarding intellectual property protection, long-simulation times, and deembedding inaccuracies of the high-speed device mount parasitics. In the presented approach, a well-defined experimental procedure is proposed to extract and validate a state-of-the-art model for a commercial noninverting output buffer in a packaged format.