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Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

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8 Author(s)
María D. Valdes-Peña ; Department of Electronic Technology , University of Vigo, 36310 Vigo, Spain ; Judit Fernández Freijedo ; María J. Moure Rodríguez ; Juan J. Rodríguez-Andina
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In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 “Burn-In Test” are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.

Published in:

IEEE Transactions on Nanotechnology  (Volume:12 ,  Issue: 4 )