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A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

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2 Author(s)
Junjie Lu ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Tennessee, Knoxville, TN, USA ; Holleman, J.

A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 5 )